#ifndef ____R_H__
#define ____R_H__

#include "ScnsConfig.h"

#if defined(SCNS_OV2640_ENABLE)&&SCNS_OV2640_ENABLE==1

#if defined(SCNS_SHORT_REG)
#error
#endif
#define SCNS_SHORT_REG

#ifndef __SCNS_OV2640_H__
#error
#endif

#ifndef __SCNS_OV2640_C_H__
#error
#endif
#define __R_QS                      0x44
#define __R_HSIZE                   0x51
#define __R_VSIZE                   0x52
#define __R_XOFFL                   0x53
#define __R_YOFFL                   0x54
#define __R_VHYX                    0x55
#define __R_DPRP                    0x56
#define __R_TEST                    0x57
#define __R_ZMOW                    0x5A
#define __R_ZMOH                    0x5B
#define __R_ZMHH                    0x5C
#define __R_BPADDR                  0x7C
#define __R_BPDATA                  0x7D
#define __R_SIZEL                   0x8C
#define __R_HSIZE8                  0xC0
#define __R_VSIZE8                  0xC1
#define __R_CTRL1                   0xC3
#define __R_MS_SP                   0xF0
#define __R_SS_ID                   0xF7
#define __R_SS_CTRL                 0xF7
#define __R_MC_AL                   0xFA
#define __R_MC_AH                   0xFB
#define __R_MC_D                    0xFC
#define __R_P_CMD                   0xFD
#define __R_P_STATUS                0xFE

#define __R_CTRLI                   0x50
#define __R_CTRLI_LP_DP             0x80
#define __R_CTRLI_ROUND             0x40

#define __R_CTRL0                   0xC2
#define __R_CTRL0_AEC_EN            0x80
#define __R_CTRL0_AEC_SEL           0x40
#define __R_CTRL0_STAT_SEL          0x20
#define __R_CTRL0_VFIRST            0x10
#define __R_CTRL0_YUV422            0x08
#define __R_CTRL0_YUV_EN            0x04
#define __R_CTRL0_RGB_EN            0x02
#define __R_CTRL0_RAW_EN            0x01

#define __R_CTRL2                   0x86
#define __R_CTRL2_DCW_EN            0x20
#define __R_CTRL2_SDE_EN            0x10
#define __R_CTRL2_UV_ADJ_EN         0x08
#define __R_CTRL2_UV_AVG_EN         0x04
#define __R_CTRL2_CMX_EN            0x01

#define __R_CTRL3                   0x87
#define __R_CTRL3_BPC_EN            0x80
#define __R_CTRL3_WPC_EN            0x40
#define __R_R_DVP_SP                0xD3
#define __R_R_DVP_SP_AUTO_MODE      0x80

#define __R_R_BYPASS                0x05
#define __R_R_BYPASS_DSP_EN         0x00
#define __R_R_BYPASS_DSP_BYPAS      0x01

#define __R_IMAGE_MODE              0xDA
#define __R_IMAGE_MODE_Y8_DVP_EN    0x40
#define __R_IMAGE_MODE_JPEG_EN      0x10
#define __R_IMAGE_MODE_YUV422       0x00
#define __R_IMAGE_MODE_RAW10        0x04
#define __R_IMAGE_MODE_RGB565       0x08
#define __R_IMAGE_MODE_HREF_VSYNC   0x02
#define __R_IMAGE_MODE_LBYTE_FIRST  0x01
#define __R_IMAGE_MODE_GET_FMT(x)   ((x)&0xC)

#define __R_REG_RESET                   0xE0
#define __R_REG_RESET_MICROC            0x40
#define __R_REG_RESET_SCCB              0x20
#define __R_REG_RESET_JPEG              0x10
#define __R_REG_RESET_DVP               0x04
#define __R_REG_RESET_IPU               0x02
#define __R_REG_RESET_CIF               0x01

#define __R_MC_BIST                 0xF9
#define __R_MC_BIST_RESET           0x80
#define __R_MC_BIST_BOOT_ROM_SEL    0x40
#define __R_MC_BIST_12KB_SEL        0x20
#define __R_MC_BIST_12KB_MASK       0x30
#define __R_MC_BIST_512KB_SEL       0x08
#define __R_MC_BIST_512KB_MASK      0x0C
#define __R_MC_BIST_BUSY_BIT_R      0x02
#define __R_MC_BIST_MC_RES_ONE_SH_W 0x02
#define __R_MC_BIST_LAUNCH          0x01

#define __R_BANK_SEL                0xFF
#define __R_BANK_SEL_DSP            0x00
#define __R_BANK_SEL_SENSOR         0x01

/* Sensor register bank FF=0x01*/

#define __R_GAIN                0x00
#define __R_COM1                0x03
#define __R_REG_PID             0x0A
#define __R_REG_VER             0x0B
#define __R_COM4                0x0D
#define __R_AEC                 0x10

#define __R_CLKRC               0x11
#define __R_CLKRC_DOUBLE        0x80
#define __R_CLKRC_2X_UXGA       (0x01 | CLKRC_DOUBLE)
#define __R_CLKRC_2X_SVGA       CLKRC_DOUBLE
#define __R_CLKRC_2X_CIF        CLKRC_DOUBLE
#define __R_CLKRC_DIVIDER_MASK  0x3F

#define __R_COM10               0x15
#define __R_HSTART              0x17
#define __R_HSTOP               0x18
#define __R_VSTART              0x19
#define __R_VSTOP               0x1A
#define __R_MIDH                0x1C
#define __R_MIDL                0x1D
#define __R_AEW                 0x24
#define __R_AEB                 0x25
#define __R_REG2A               0x2A
#define __R_FRARL               0x2B
#define __R_ADDVSL              0x2D
#define __R_ADDVSH              0x2E
#define __R_YAVG                0x2F
#define __R_HSDY                0x30
#define __R_HEDY                0x31
#define __R_ARCOM2              0x34
#define __R_REG45               0x45
#define __R_FLL                 0x46
#define __R_FLH                 0x47
#define __R_COM19               0x48
#define __R_ZOOMS               0x49
#define __R_COM22               0x4B
#define __R_COM25               0x4E
#define __R_BD50                0x4F
#define __R_BD60                0x50
#define __R_REG5D               0x5D
#define __R_REG5E               0x5E
#define __R_REG5F               0x5F
#define __R_REG60               0x60
#define __R_HISTO_LOW           0x61
#define __R_HISTO_HIGH          0x62

#define __R_REG04               0x04
#define __R_REG04_DEFAULT       0x28
#define __R_REG04_HFLIP_IMG     0x80
#define __R_REG04_VFLIP_IMG     0x40
#define __R_REG04_VREF_EN       0x10
#define __R_REG04_HREF_EN       0x08
#define __R_REG04_SET(x)        (REG04_DEFAULT|x)

#define __R_REG08               0x08
#define __R_COM2                0x09
#define __R_COM2_STDBY          0x10
#define __R_COM2_OUT_DRIVE_1x   0x00
#define __R_COM2_OUT_DRIVE_2x   0x01
#define __R_COM2_OUT_DRIVE_3x   0x02
#define __R_COM2_OUT_DRIVE_4x   0x03

#define __R_COM3                0x0C
#define __R_COM3_DEFAULT        0x38
#define __R_COM3_BAND_50Hz      0x04
#define __R_COM3_BAND_60Hz      0x00
#define __R_COM3_BAND_AUTO      0x02
#define __R_COM3_BAND_SET(x)    (COM3_DEFAULT|x)

#define __R_COM7                0x12
#define __R_COM7_SRST           0x80
#define __R_COM7_RES_UXGA       0x00 /* UXGA */
#define __R_COM7_RES_SVGA       0x40 /* SVGA */
#define __R_COM7_RES_CIF        0x20 /* CIF  */
#define __R_COM7_ZOOM_EN        0x04 /* Enable Zoom */
#define __R_COM7_COLOR_BAR      0x02 /* Enable Color Bar Test */
#define __R_COM7_GET_RES(x)     ((x)&0x70)

#define __R_COM8                0x13
#define __R_COM8_DEFAULT        0xC0
#define __R_COM8_BNDF_EN        0x20 /* Enable Banding filter */
#define __R_COM8_AGC_EN         0x04 /* AGC Auto/Manual control selection */
#define __R_COM8_AEC_EN         0x01 /* Auto/Manual Exposure control */
#define __R_COM8_SET(x)         (COM8_DEFAULT|x)
#define __R_COM8_SET_AEC(r,x)   (((r)&0xFE)|((x)&1))

#define __R_COM9                0x14 /* AGC gain ceiling */
#define __R_COM9_DEFAULT        0x08
#define __R_COM9_AGC_GAIN_2x    0x00 /* AGC:    2x */
#define __R_COM9_AGC_GAIN_4x    0x01 /* AGC:    4x */
#define __R_COM9_AGC_GAIN_8x    0x02 /* AGC:    8x */
#define __R_COM9_AGC_GAIN_16x   0x03 /* AGC:   16x */
#define __R_COM9_AGC_GAIN_32x   0x04 /* AGC:   32x */
#define __R_COM9_AGC_GAIN_64x   0x05 /* AGC:   64x */
#define __R_COM9_AGC_GAIN_128x  0x06 /* AGC:  128x */
#define __R_COM9_AGC_SET(x)     (COM9_DEFAULT|(x<<5))

#define __R_CTRL1_AWB           0x08 /* Enable AWB */

#define __R_VV                  0x26
#define __R_VV_AGC_TH_SET(h,l)  ((h<<4)|(l&0x0F))

#define __R_REG32               0x32
#define __R_REG32_UXGA          0x36
#define __R_REG32_SVGA          0x09
#define __R_REG32_CIF           0x00

#define __R_VAL_SET(x,mask,rshift,lshift) ((((x) >> rshift) & mask) << lshift)

#define __R_CTRLI_V_DIV_SET(x)      VAL_SET(x, 0x3, 0, 3)
#define __R_CTRLI_H_DIV_SET(x)      VAL_SET(x, 0x3, 0, 0)

#define __R_SIZEL_HSIZE8_11_SET(x)  VAL_SET(x, 0x1, 11, 6)
#define __R_SIZEL_HSIZE8_SET(x)     VAL_SET(x, 0x7, 0, 3)
#define __R_SIZEL_VSIZE8_SET(x)     VAL_SET(x, 0x7, 0, 0)

#define __R_HSIZE8_SET(x)           VAL_SET(x, 0xFF, 3, 0)
#define __R_VSIZE8_SET(x)           VAL_SET(x, 0xFF, 3, 0)

#define __R_HSIZE_SET(x)            VAL_SET(x, 0xFF, 2, 0)
#define __R_VSIZE_SET(x)            VAL_SET(x, 0xFF, 2, 0)

#define __R_XOFFL_SET(x)            VAL_SET(x, 0xFF, 0, 0)
#define __R_YOFFL_SET(x)            VAL_SET(x, 0xFF, 0, 0)

#define __R_VHYX_VSIZE_SET(x)       VAL_SET(x, 0x1, (8+2), 7)
#define __R_VHYX_HSIZE_SET(x)       VAL_SET(x, 0x1, (8+2), 3)
#define __R_VHYX_YOFF_SET(x)        VAL_SET(x, 0x3, 8, 4)
#define __R_VHYX_XOFF_SET(x)        VAL_SET(x, 0x3, 8, 0)

#define __R_TEST_HSIZE_SET(x)       VAL_SET(x, 0x1, (9+2), 7)

#define __R_ZMOW_OUTW_SET(x)        VAL_SET(x, 0xFF, 2, 0)
#define __R_ZMOH_OUTH_SET(x)        VAL_SET(x, 0xFF, 2, 0)

#define __R_ZMHH_ZSPEED_SET(x)      VAL_SET(x, 0x0F, 0, 4)
#define __R_ZMHH_OUTH_SET(x)        VAL_SET(x, 0x1, (8+2), 2)
#define __R_ZMHH_OUTW_SET(x)        VAL_SET(x, 0x3, (8+2), 0)
#define __R_CIF_WIDTH                   (400)
#define __R_CIF_HEIGHT                  (296)
#define __R_SVGA_WIDTH                  (800)
#define __R_SVGA_HEIGHT                 (600)
#define __R_UXGA_WIDTH                  (1600)
#define __R_UXGA_HEIGHT                 (1200)
#define __R_SVGA_HSIZE                  (800)
#define __R_SVGA_VSIZE                  (600)
#define __R_UXGA_HSIZE                  (1600)
#define __R_UXGA_VSIZE                  (1200)
#endif
#endif
